1. Field of the Invention
The present invention relates to the field of semiconductor processing, and more particularly to a MOS Transistor including a gate dielectric stack comprised of materials having various dielectric constants to produce a graded dielectric stack.
2. Description of the Relevant Art
The fabrication of MOS (metal-oxide-semiconductor) transistors is well known. Typically, a silicon substrate is divided into a plurality of active and isolation regions through an isolation process. After appropriate cleaning of the substrate surface, a thin gate oxide is then grown on an upper surface of the substrate over the active regions. Next, a plurality of polysilicon gates are formed on the gate oxide layer. Each gate traverses an active region of the substrate thereby effectively dividing the active region into a pair of regions referred to as source/drain regions. After formation of the polysilicon gates, the source/drain regions are implanted with an impurity concentration sufficient to render the source/drain regions conductive. The implantation of the source/drain regions after the formation of the polysilicon gate insures that the gate is self aligned to the source/drain regions and, consequently, to the device channel region as well.
As transistor channel lengths fall below 0.5 microns, the limitations of conventional transistor processing become more apparent. In particular, short channel effects emerge as a problem for transistors with channel lengths of less than approximately 2 microns. For devices of this size, the depletion regions around the negatively biased drain/substrate and source/substrate junctions during normal circuit operation begin to approach a size comparable to the channel length. Under these circumstances, the transistor drain current fails to saturate (i.e., the drain current is a function of drain voltage regardless of the drain voltage value), sub-threshold leakage begins to exhibit a dependence on the drain voltage, and the threshold voltage exhibits dependence on the transistor geometries and the specific biasing conditions. From experimental data, it has been observed that the onset of short channel behavior is, to a first order approximation for a given starting material under a given set of biasing conditions, a function of the junction depth and the thickness of the gate oxide. See, e.g., Sze, Physics of Semiconductor Devices p. 471 (Wiley & Sons 1981). Accordingly, semiconductor manufacturers typically attempt to simply scale the dimensions of these parameters to achieve smaller channel length devices without incurring significant short channel behavior.
The preceding discussion indicates that increasingly thin gate oxide films are required to maintain adequate performance in deep sub-micron transistors. Thin gate oxides, however, are difficult to consistently manufacture and are susceptible to reliability problems. Typically, the maximum electric field that may be sustained across an oxide film without resulting in oxide breakdown is in the vicinity of approximately 6 MV/cm. If a particular process is designed to operate with a 3.3 V gate voltage, oxide films of less than approximately 55 angstroms in thickness may be susceptible to reliability problems. This minimum oxide thickness imposes a significant restraint on transistor performance in the deep sub-micron region.
In addition to manufacturing and reliability concerns presented by thin oxides, the migration of mobile contaminants across the gate oxide film and into active regions of the device increases as oxide thickness decreases. This problem is especially acute for boron implanted gate structures typically associated with p-channel transistors because of the relatively high rate at which boron atoms tend to diffuse through an oxide film. Because boron atoms are p-type dopants in a silicon lattice, excessive boron migration into the channel region of the transistor can result in a measurable and undesirable shift in threshold voltage for p-channel transistors.
Therefore, it would be highly desirable to implement a process for manufacturing MOS transistors that eased the concerns associated with thin oxide films without degrading transistor performance or subthreshold leakage.